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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 6 1 publication order number: NB3F8L3010C/d NB3F8L3010C 3.3v / 2.5v / 1.8v / 1.5v 3:1:10 lvcmos fanout buffer description the NB3F8L3010C is a 3:1:10 clock / data fanout buffer operating on a 3.3 v / 2.5 v core v dd and two flexible 3.3 v / 2.5 v / 1.8 v / 1.5 v vddo n supplies which must be equal or less than v dd . a mux selects between a crystal input, or either of two differential/se clock / data inputs. differential inputs accept lvpecl, lvds, hcsl, or sstl and single?ended levels. the mux control lines, sel0 and sel1, select clk0/clk0 , clk1/clk1 , or crystal input pins per table 3. the crystal input is disabled when a clock input is selected. output enable pin, oe, synchronously forces a high impedance state (hz) when low per table 4. outputs consist of 10 single?ended lvcmos outputs. features ? ten cmos / lvttl outputs up to 200 mhz ? differential inputs accept lvpecl, lvds, hcsl, or sstl ? crystal oscillator interface ? crystal input frequency range: 10 mhz to 50 mhz ? output skew: 10 ps typical ? additive rms phase jitter @ 125 mhz, (12 khz ? 20 mhz): 0.03 ps (typical) ? synchronous output enable ? output defined level when input is floating ? power supply modes: ? single 3.3 v ? single 2.5 v ? mixed 3.3 v 5% core/2.5 v 5% output operating supply ? mixed 3.3 v 5% core/1.8 v 0.2 v output operating supply ? mixed 3.3 v 5% core/1.5 v 0.15 v output operating supply ? mixed 2.5 v 5% core/ 1.8 v 0.2 v output operating supply ? mixed 2.5 v 5% core /1.5 v 0.15 v output operating supply ? two separate output bank power supplies ? industrial temp. range -40 c to 85 c ? these are pb?free devices applications ? clock distribution ? networking and communications ? high end computing ? wireless and wired infrastructure end products ? servers ? ethernet switch/routers ? at e ? test and measurement marking diagram qfn32 g suffix case 488am www. onsemi.com see detailed ordering and shipping information page 12 of this data sheet. ordering information a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package 32 1 nb3f8l 3010c awlyywwg 1
NB3F8L3010C www. onsemi.com 2 figure 1. simplified logic diagram q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 vdd vddoa vddob gnd sel0 sel1 clk0 clk1 xtal_in xtal_out oe sync osc clk1 clk0 bank a bank b figure 2. pinout configuration (top view) clk1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 exposed pad (ep) NB3F8L3010C q0 vddoa q1 gnd q2 vddoa q3 q4 q9 vddob q8 gnd q7 vddob q6 q5 gnd oe sel0 sel1 clk1 gnd gnd clk0 gnd gnd clk0 xtal_out xtal_in vdd gnd
NB3F8L3010C www. onsemi.com 3 table 1. pin description number name type input default description 1, 3, 5, 7, 8 q0, q1, q2, q3, q4 lvcmos outputs ? bank a 17, 18, 20, 22, 24 q5, q6, q7, q8, q9 lvcmos outputs ? bank b 2, 6 vddoa power positive supply pins for bank a outputs q0 ? q4 19, 23 vddob power positive supply pins for bank b outputs q5 ? q9 4, 9, 15, 16, 21, 25, 26, 32 gnd gnd ground supply 10 vdd power v dd positive supply pin for core and inputs. 11 xtal_in xtal osc / clk input crystal oscillator interface or external clock source at lvcmos levels 12 xtal_out xtal osc output crystal oscillator interface 13 clk0 diff / se input pulldown non-inverting clock/data input 0. 14 clk0 diff / se input pullup / pulldown inverting differential clock input 0. 27 clk1 diff / se input pullup / pulldown inverting differential clock input 1 28 clk1 diff / se input pulldown non-inverting clock/data input 1 29 sel1 lvcmos / lvttl input pulldown input clock select. see table 3 for function. input pulldown 30 sel0 lvcmos / lvttl input pulldown input clock select. see table 3 for function. input pulldown 31 oe lvcmos / lvttl input pulldown output enable control. see table 4 for function. ? ep ? the exposed pad (ep) on the qfn?32 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat? sinking conduit. the pad is electrically connected to the die, and must be electrically connected to gnd. 1. all vdd, vddo n and gnd pins must be externally connected to a power supply to guarantee proper operation. bypass each v dd and vddo n with 0.01 f cap to gnd. table 2. pin characteristics symbol parameter min typ max unit c in input capacitance 4 pf r input pulldown resistor; input pulldown resistor 50 k c pd power dissipation capacitance (per output) vddo = 3.3 v vddo = 2.5 v vddo = 1.8 v vddo = 1.5 v pf r out output impedance vddo = 3.3 v vddo = 2.5 v vddo = 1.8 v vddo = 1.5 v 20
NB3F8L3010C www. onsemi.com 4 function tables table 3. clock enable (selx) function table sel[1:0] input selected input clock 00 clk0/clk0 01 clk1/clk1 10 crystal osc input 11 crystal osc input table 4. clock output enable (oe) function table oe input q[9:0] output 0 high impedance 1 outputs enabled table 5. diff in/out table (diff or s.e.) input condition output clk0/1; clk0/1 = open logic low clk0/1; clk0/1 = gnd undefined clk0/1 = high; clk0/1 = low logic high clk0/1 = low; clk0/1 = high logic low table 6. crystal characteristics parameter min typ max unit mode of oscillation fundamental frequency 10 50 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf drive power 100 w table 7. attributes characteristic value esd protection human body model machine model >2 kv 200 v moisture sensitivity (note 2) qfn32 level 3 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 474 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 8. maximum ratings (note 3) symbol parameter condition rating unit v dd , vddo n positive power supply gnd = 0 v 4.6 v v i input voltage xtal_in diff, selx, oe inputs 0 v i v dd ?0.5 v i v dd + 0.5 v v o output voltage ? 0.5 v o vddo n + 0.5 v t a operating temperature range, industrial ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm 31 27 c/w jc thermal resistance (junction?to?case) (note 3) 12 c/w stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
NB3F8L3010C www. onsemi.com 5 table 9. power supply dc characteristics v dd = 3.3 v 5% (3.135 v to 3.465 v) or v dd = 2.5 v 5% (2.375 v to 2.625 v) and vddo n = 3.3 v 5% (3.135 v to 3.465 v) or 2.5 v 5% (2.375 v to 2.625 v) or 1.8 v 0.2 v (1.6 v to 2.0 v) or 1.5 v 0.15 v (1.35 v to 1.65 v); t a = ?40 c to 85 c symbol parameter test conditions min typ max unit idd vdd power supply current oe = 0, no load 3.3 v 5%; vddo n = 3.3 v 5% or 2.5 v 5% or 1.8 v 0.2 v or 1.5 v 0.15 v 2.5 v 5%; vddo n = 2.5 v 5% or 1.8 v 0.2 v or 1.5 v 0.15 v 30 50 ma iddo vddo power supply current oe = 0, no load 3.3 v 5%; vddo n = 3.3 v 5% or 2.5 v 5% or 1.8 v 0.2 v or 1.5 v 0.15 v 2.5 v 5%; vddo n = 2.5 v 5% or 1.8 v 0.2 v or 1.5 v 0.15 v 5 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. table 10. dc characteristics t a = ?40 c to 85 c symbol parameter test conditions min typ max unit v ih lvcmos / lvttl input high voltage (oe, selx) v dd = 3.3 v 5% v dd = 2.5 v 5% 2 1.7 v dd + 0.3 v dd + 0.3 v v il lvcmos / lvttl input low voltage (oe, selx) v dd = 3.3 v 5% v dd = 2.5 v 5% ?0.3 ?0.3 0.8 0.7 v i ih input high current oe, selx, clkx/clkx v dd = v in = 3.465 v v dd = v in = 3.465 v or 2.625 v 150 150 a i il input low current oe, selx clkx clkx v dd = 3.465 v; v in = 0.0 v v dd = 3.465 v or 2.625 v v in = 0.0 v v dd = 3.465 v or 2.625 v v in = 0.0 v ?5 ?5 ?150 a v oh output high voltage (note 4) vddo n = 3.3 v 5% 2.6 v vddo n = 2.5 v 5% 1.8 vddo n = 1.8 v 0.2 v 1.2 vddo n = 1.5 v 0.15 v 0.9 v ol output low voltage (note 4) vddo n = 3.3 v 5% or 2.5 v 5% 0.5 v vddo n = 1.8 v 0.2 v 0.4 vddo n = 1.5 v 0.15 v 0.37 v pp peak?to?peak input voltage v il > ?0.3 v clkx/clkx v dd = 3.3 v 5% or v dd = 2.5 v 5% 0.15 1.3 v v ihcmr input high level common mode range v cm = v ih ; v il > ?0.3 v clkx/clkx v dd = 3.3 v 5% or v dd = 2.5 v 5% 0.5 v dd ? 0.85 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. 4. outputs terminated with 50 to vddo n /2. see parameter measurement information.. table 11. ac characteristics v dd = 3.3 v 5% (3.135 v to 3.465 v) or v dd = 2.5 v 5% (2.375 v to 2.625 v) and vddo n = 3.3 v 5% (3.135 v to 3.465 v) or 2.5 v 5% (2.375 v to 2.625 v) or 1.8 v 0.2 v (1.6 v to 2.0 v) or 1.5 v 0.15 v (1.35 v to 1.65 v); t a = ?40 c to 85 c symbol parameter test conditions min typ max unit f max output frequency using external crystal 10 50 mhz using external clock source (note 5) dc 200 mhz
NB3F8L3010C www. onsemi.com 6 table 11. ac characteristics v dd = 3.3 v 5% (3.135 v to 3.465 v) or v dd = 2.5 v 5% (2.375 v to 2.625 v) and vddo n = 3.3 v 5% (3.135 v to 3.465 v) or 2.5 v 5% (2.375 v to 2.625 v) or 1.8 v 0.2 v (1.6 v to 2.0 v) or 1.5 v 0.15 v (1.35 v to 1.65 v); t a = ?40 c to 85 c symbol unit max typ min test conditions parameter t sk(o) output skew (notes 6 and 7) 10 55 ps t jitter additive rms phase jitter (integrated 12 khz 20 mhz) (note 8) input clock from clk0/clk0 or clk1/clk1 vddo n = 3.3 v 5% 0.03 ps vddo n = 2.5 v 5% 0.03 vddo n = 1.8 v 0.2 v 0.03 vddo n = 1.5 v 0.15 v 0.03 external clock over drives crystal interface vddo n = 3.3 v 5% 0.03 vddo n = 2.5 v 5% 0.03 vddo n = 1.8 v 0.2 v 0.03 vddo n = 1.5 v 0.15 v 0.03 input clock from crystal vddo n = 3.3 v 5% 0.03 vddo n = 2.5 v 5% 0.03 vddo n = 1.8 v 0.2 v 0.03 vddo n = 1.5 v 0.15 v 0.03 t r / t f output rise/fall time (20% and 80%) vddo n = 3.3 v 5% 150 350 500 ps vddo n = 2.5 v 5% 150 350 500 vddo n = 1.8 v 0.2 v 150 350 600 vddo n = 1.5 v 0.15 v 150 350 600 odc output duty cycle vddo n = 3.3 v 5% 45 55 % vddo n = 2.5 v 5% 40 60 vddo n = 1.8 v 0.2 v 40 60 vddo n = 1.5 v 0.15 v 40 60 t en output enable time (note 9) oe 4 cycles t dis output disable time (note 9) oe 4 cycles mux_ isolation mux_ isolation 155.52 mhz 55 db note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. 5. xtal_in can be overdriven relative to a signal a crystal would provide. 6. defined as skew between outputs at the same supply voltage and with equal load conditions. measured at vddo n /2. 7. this parameter is defined in accordance with jedec standard 65. 8. see phase noise plot. 9. these parameters are guaranteed by characterization. not tested in production. see parameter measurement information
NB3F8L3010C www. onsemi.com 7 parameter measurement information 3.3 v core / 3.3 v output load ac test circuit (terminating to vddo n /2) 2.5 v core / 2.5 v output load ac test circuit (terminating to vddo n /2) 3.3 v core / 2.5 v output load ac test circuit (terminating to vddo n /2) 3.3 v core / 1.8 v output load ac test circuit (terminating to vddo n /2) 3.3 v core / 1.5 v output load ac test circuit (terminating to vddo n /2) 2.5 v core / 1.8 v output load ac test circuit (terminating to vddo n /2) 2.5 v core / 1.5 v output load ac test circuit (terminating to vddo n /2) 50 z = 50 scope lvcmos qx v dd = +1.65 v 5% vddo n = v dd = +1.65 v 5% gnd = +1.65 v 5% 50 z = 50 scope lvcmos qx v dd = +1.25 v 5% vddo n = v dd = +1.25 v 5% gnd = +1.25 v 5% 50 z = 50 scope lvcmos qx v dd = +2.05 v 5% vddo n = +1.25 v 5% gnd = +1.25 v 5% 50 z = 50 scope lvcmos qx v dd = +2.4 v 5% vddo n = +0.9 v 0.1 v gnd = +0.9 v 0.1 v 50 z = 50 scope lvcmos qx v dd = +2.55 v 5% vddo n = +0.75 v 0.15 v gnd = +0.75 v 0.15 v 50 z = 50 scope lvcmos qx v dd = +1.6 v 5% vddo n = +0.9 v 0.1 v gnd = +0.9 v 0.1 v 50 z = 50 scope lvcmos qx v dd = +1.75 v 5% vddo n = +0.75 v 0.15 v gnd = +0.75 v 0.5 v figure 3. operational supply and termination test conditions
NB3F8L3010C www. onsemi.com 8 parameter measurement information differential input level within device output skew output enable /disable (oe high = enabled) output duty cycle / pulse width / period output rise/fall time mux isolation x point v cmr v pp v dd clk clk gnd vddo n /2 vddo n /2 t sk(0) q x q v v dd /2 t dis vddo n /2 t en v dd v oh v ol vddo n /2 0 v oe q x vddo n /2 t pw t period q x odc = (t pw / t period ) x 100% q x t r t f 80% 80% spectrum of o utput signal qx mux selects active inpu t clock signal mux = a0 - a1 mux selects static input fc (fundamental) amplitud e (db) frequ ency (hz) a0 a1 _isol figure 4. operational waveforms and mux input isolation plot 20% 20% application information recommendations for unused lvcmos output pins inputs: clk/clk inputs for applications not requiring the use of the differential input, both clk and clk can be left floating. though not required, but for additional protection, a 1 k resistor can be tied from clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1 k resistor can be tied from xtal_in to ground. lvcmos outputs a 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1 k resistor can be used. power supplies vdd is the power supply for the core and input circuitry. vddoa and vddob are two separate positive power supplies for two banks of outputs: vddoa pins 2 and 6 are connected internally for outputs q0 ? q4. vddob pins 19 and 23 are connected internally for outputs q5 ? q9.
NB3F8L3010C www. onsemi.com 9 differential input with single?ended interconnect refer to figure 5 to interconnect a single?ended to a differential pair of inputs. the reference bias voltage v ref = v dd /2 is generated by the resistor divider of r3 and r4. bypass capacitor (c1) can filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. adjust r1 and r2 to common mode voltage of the signal input swing to preserve duty cycle. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination by r1 and r2 will attenuate the signal amplitude in half. termination may be done by using rs or by using r1 and r2. first, rs = 0 and then r3 and r4 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . the differential input can handle full rail lvcmos signaling, but it is recommended that the amplitude be reduced. the datasheet specifies a differential amplitude which needs to be doubled for a single ended equivalent stimulus. v ilmin cannot be less than ?0.3 v and v ihmax cannot be more than v dd + 0.3 v. the datasheet specifications are characterized and guaranteed by using a differential signal. z o = 50 single c1 0.1 f r2 100 z 0 = r o + r s gnd = 0.0 v dd r1 100 r s r o ended driver gnd = 0.0 v dd gnd = 0.0 r4 1 k r3 1 k differential in v dd clkx clkx figure 5. differential input with single?ended interconnect crystal input interface the device has been characterized with 18 pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 6 below as 15 pf were determined using an 18 pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 6. crystal input interface clock overdriving the xtal interface the xtal_in input can accept a single?ended l vcmos signal through an ac coupling capacitor. a general lvcmos interface diagram is shown in figure 7 and a general lvpecl interface in figure 8. the xtal_out pin must be left floating. the maximum amplitude of the input signal should not exceed 2 v and the input edge rate can be as slow as 10 ns. this configuration requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal.
NB3F8L3010C www. onsemi.com 10 figure 7. general diagram for lvcmos driver to xtal input interface use rs or r1 / r2 figure 8. general diagram for lvpecl driver to xtal input interface z o = 50 lvmos c1 0.1 f r2 100 z 0 = r o + r s gnd = 0.0 v v dd r1 100 r s r o gnd = 0.0 v xtal_in v dd xtal_out z o = 50 lvpecl c1 0.1 f v tt = v dd ? 2.0 v v dd gnd = 0.0 v xtal_in xtal_out z o = 50 50 50
NB3F8L3010C www. onsemi.com 11 differential clock input interface the clk / clk accept lvds, lvpecl, sstl, hcsl differential signals. signals must meet the v pp and vcmr input requirements. figures 9 to 13 show interface examples for the clk / clk input with built?in 50 terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 9. clk / clk input driven by 3.3 v lvpecl driver (thevenin parallel termination) figure 10. clk / clk input driven by 3.3 v lvpecl driver (?y? parallel termination) figure 11. clk / clk input driven by a 3.3 v hcsl driver figure 12. clk / clk input driven by 3.3 v lvds driver figure 13. clk / clk input driven by 2.5 v sstl driver z o = 50 lvpecl 84 gnd = 0.0 v 84 z o = 50 differential in q x q x clkx clkx z o = 50 lvpecl 50 gnd = 0.0 v 50 z o = 50 differential in q x q x clkx clkx v dd = +3.3 v 125 125 gnd = 0.0 v v dd = +3.3 v gnd = 0.0 v v dd = +3.3 v 50 gnd = 0.0 v v dd = +3.3 v gnd = 0.0 v v dd = +3.3 v z o = 50 hcsl 50 gnd = 0.0 v 50 z o = 50 differential in q x q x clkx clkx gnd = 0.0 v v dd = +3.3 v gnd = 0.0 v v dd = +3.3 v 33 (opt) 33 (opt) z o = 50 sstl 120 gnd = 0.0 v 120 z o = 50 differential in q x q x clkx clkx v dd = +2.5 v 120 120 gnd = 0.0 v v dd = +3.3 v gnd = 0.0 v v dd = +2.5 v z o = 50 lvds 100 z o = 50 differential in q x q x clkx clkx gnd = 0.0 v v dd = +3.3 v gnd = 0.0 v v dd = +3.3 v
NB3F8L3010C www. onsemi.com 12 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 14 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to ef fectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) is application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13 mils (0.30 to 0.33 mm) with 1 oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. figure 14. suggested assembly for exposed pad thermal release path ? cut?away view (not to scale) ordering information device package shipping ? NB3F8L3010Cmng qfn32 (pb?free) 74 units / rail NB3F8L3010Cmnr4 g qfn32 (pb?free) 1000 / tape & reel NB3F8L3010Cmntw g qfn32 (pb?free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3F8L3010C www. onsemi.com 13 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NB3F8L3010C/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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